Digital electronic devices typically comprise a large number of circuit elements, all of which generally need to operate satisfactorily in order for the devices to work correctly. Basically, a digital device comprises a number of storage elements, such as flip-flops and registers which store digital information, which are interconnected by processing elements, which perform processing operations in connection with the information in a series of processing steps controlled by one or more clock signals. The particular processing operations that are performed by the processing elements in connection with information in one storage element may be as simple as, for example, transferring the information contained in one the storage element to another storage element. Alternatively, the processing elements may perform quite complex processing operations, representing a complex mathematical or other transformation of the information. In addition, particular processing elements may perform processing operations which are predetermined and fixed, or they may perform a variety of types of processing operations determined by digital information which, in turn, may be stored in ones of the storage elements which are provided to control the processing elements. Generally, the collection of processing elements comprising a device defines the device's state, which state can be modified by successive ticks of the clocking signal(s).
A variety of methodologies have been developed and used over the years to assist in verifying that digital devices were operating correctly, and if not provide guidance as to which components should be repaired or replaced to provide correct operation. Recently, a test methodology has been developed whereby state information is scanned into a device to place the device in a particular state. In the scanning operation, all of the information storage elements, including all of the flip-flops and registers in the device or in a component under test, are effectively connected in series and an input "vector" scanned in. After the device's state has been established, the clocking signal or signals controlling the device is or are advanced, allowing the processing elements to process the digital information defining the scanned-in state and the processed input state to be stored by the storage elements. The actual state vector defining the state at that point is then scanned out, and compared to an expected state vector representing the state vector which would be expected if the device were operating properly. If actual state vector corresponds to the expected state vector, the device will generally be considered to be operating properly. On the other hand, if the actual state vector does not correspond to the expected state vector, the device will be considered to not be operating properly, and the particular locations along the actual and expected state vectors at which they differ can be useful in determining and locating the malfunction.
Generally, a problem arises in using the scan test methodology in connection with digital devices which have multiple clock domains, that is, devices comprising a plurality of sections controlled by clock signals of different frequencies. Generally, if information is to be transferred between sections controlled by clock signals of different frequencies, synchronizing elements, such as delay elements, need to be provided to synchronize the transfers to avoid loss of information across the interface between the sections. Such synchronizing elements tend to increase the component count, which can also complicate component layout, particularly on integrated circuits, since the series of circuit elements through which the scan vector is scanned is arbitrary and can pass between the clock domains any number of times. In addition, particularly in connection with layout of integrated circuits, typically the sequence of the circuit elements comprising the scan chain for an integrated circuit is determined towards the end of the process of laying out components on the integrated circuit, in which case providing synchronizing elements along the scan chain can complicate the layout process.